Self aligned method of forming a semiconductor memory array of floating gate memory cells with vertical control gate sidewalls and insulation spacers, and a memory array made thereby

ABSTRACT

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. Control gates are each formed with a substantially vertical face portion by covering a portion of a conductive layer with a protective layer, and performing an anisotropic etch to remove the exposed portion of the conductive layer. An insulation sidewall spacer is formed against the vertical face portion. The control gates have protruding portions that extend over the floating gates.

PRIORITY

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/283,110, filed Apr. 10, 2001, and entitled Method toForm Vertical Word Line Side Wall For Self-Aligned NVM Cells.

TECHNICAL FIELD

[0002] The present invention relates to a self-aligned method of forminga semiconductor memory array of floating gate memory cells of the splitgate type. The present invention also relates to a semiconductor memoryarray of floating gate memory cells of the foregoing type.

BACKGROUND OF THE INVENTION

[0003] Non-volatile semiconductor memory cells using a floating gate tostore charges thereon and memory arrays of such non-volatile memorycells formed in a semiconductor substrate are well known in the art.Typically, such floating gate memory cells have been of the split gatetype, or stacked gate type, or a combination thereof.

[0004] One of the problems facing the manufacturability of semiconductorfloating gate memory cell arrays has been the alignment of the variouscomponents such as source, drain, control gate, and floating gate. Asthe design rule of integration of semiconductor processing decreases,reducing the smallest lithographic feature, the need for precisealignment becomes more critical. Alignment of various parts alsodetermines the yield of the manufacturing of the semiconductor products.

[0005] Self-alignment is well known in the art. Self-alignment refers tothe act of processing one or more steps involving one or more materialssuch that the features are automatically aligned with respect to oneanother in that step processing. Accordingly, the present invention usesthe technique of self-alignment to achieve the manufacturing of asemiconductor memory array of the floating gate memory cell type.

[0006] In the split-gate architecture, the memory cells can be formed inmirrored pairs. FIG. 1A illustrates a partially formed pair of memorycells, with floating gates 1 disposed over a substrate 2. A sourceregion 3 is formed in the substrate 2, and is electrically connected toa source line 4. Layers of insulating materials 5 insulate floating gate1, substrate 2, source regions 3 and source line 4 from each other.Control gates are formed by first forming a layer 6 of conductivematerial (such as polysilicon) over the structure, as shown in FIG. 1A.An anisotropic poly etch is then performed to remove layer 5 except forspacer portions that form the control gates, as illustrated in FIG. 2B.The problem with this configuration is that the control gate spacers 6have sloped side wall profiles 7 that are difficult to insulate so theremaining features of the memory cells (such as drain region andelectrical contacts connected thereto) can be formed. As illustrated inFIG. 3C, insulation spacers 8 can be formed against part of the slopedsidewall portion, but most of the sloped side wall portions of controlgates 6 are still exposed.

[0007] There is a need for a memory cell fabrication process thatfacilitates the insulation of the control gate sidewalls.

SUMMARY OF THE INVENTION

[0008] The present invention addresses the aforementioned needs byproviding a self-aligned method of forming a semiconductor memory arrayof floating gate memory cells in a semiconductor substrate, where eachmemory cell has a floating gate, a first terminal, a second terminalwith a channel region therebetween, and a control gate. The methodincludes the steps of:

[0009] a) forming a plurality of spaced apart isolation regions on thesubstrate which are substantially parallel to one another and extend ina first direction, with an active region between each pair of adjacentisolation regions, the active regions each comprising a first layer ofinsulation material on the semiconductor substrate and a first layer ofconductive material on the first layer of insulation material;

[0010] b) forming a plurality of spaced apart blocks of insulationmaterial in each of the active regions and over the first layer ofconductive material;

[0011] c) forming a plurality of spaced apart blocks of conductivematerial in each of the active regions that are each disposed over andinsulated from the substrate and adjacent to one of the blocks ofinsulation material;

[0012] d) forming a protective layer of material over a first portion ofeach of the blocks of conductive material, wherein a second portion ofeach of the blocks of conductive material is left uncovered by the layerof protective material;

[0013] e) etching away the second portions of the blocks of conductivematerial to form a substantially vertical sidewall portion on each ofthe blocks of conductive material;

[0014] f) forming a plurality of first terminals in the substrate,wherein in each of the active regions each of the first terminals has aside edge that is aligned to one of the substantially vertical sidewallportions; and

[0015] g) forming a plurality of second terminals in the substrate,wherein in each of the active regions each of the second terminals isspaced apart from the first terminals.

[0016] In another aspect of the present invention, the method includesthe steps of:

[0017] a) forming a plurality of spaced apart isolation regions on thesubstrate which are substantially parallel to one another and extend ina first direction, with an active region between each pair of adjacentisolation regions, the active regions each comprising a first layer ofinsulation material on the semiconductor substrate and a first layer ofconductive material on the first layer of insulation material;

[0018] b) forming a plurality of spaced apart first trenches across theactive regions and isolation regions which are substantially parallel toone another and extend in a second direction that is substantiallyperpendicular to the first direction and exposing the first layer of theconductive material in each of the active regions;

[0019] c) forming first side wall spacers of a material on side walls ofthe first trenches;

[0020] d) forming a second side wall spacer of a material on each of thefirst side wall spacers;

[0021] e) forming second trenches in each of the active regions adjacentto the first trenches, wherein the formation of the second trenchesincludes removing the first side wall spacers;

[0022] f) filling each of the second trenches with a second conductivematerial to form blocks of conductive material;

[0023] g) forming a protective layer of material over a first portion ofeach of the blocks of conductive material, wherein a second portion ofeach of the blocks of conductive material is left uncovered by the layerof protective material;

[0024] h) etching away the second portions of the blocks of conductivematerial to form a substantially vertical sidewall portion on each ofthe blocks of conductive material;

[0025] i) forming a plurality of first terminals in the substrate,wherein in each of the active regions each of the first terminals has aside edge that is aligned to one of the substantially vertical sidewallportions; and

[0026] j) forming a plurality of second terminals in the substrate,wherein in each of the active regions each of the second terminals isspaced apart from the first terminals.

[0027] In yet another aspect of the present invention, an electricallyprogrammable and erasable memory device includes a substrate ofsemiconductor material of a first conductivity type, first and secondspaced-apart regions in the substrate of a second conductivity type witha channel region therebetween, a first insulation layer disposed oversaid substrate, an electrically conductive floating gate disposed oversaid first insulation layer and extending over a portion of the channelregion and over a portion of the first region, a second insulation layerdisposed over and adjacent the floating gate and having a thicknesspermitting Fowler-Nordheim tunneling of charges therethrough, anelectrically conductive control gate having a first portion disposedadjacent to and insulated from the floating gate and a second portionextending over a portion of the second insulation layer and a portion ofthe floating gate, the control gate having a substantially verticalsidewall portion, and an insulation spacer formed adjacent to thesubstantially vertical sidewall portion of the control gate. The secondregion has an edge that is aligned with the substantially verticalsidewall portion.

[0028] In yet one more aspect of the present invention, an electricallyprogrammable and erasable memory device includes a substrate ofsemiconductor material of a first conductivity type, first and secondspaced-apart regions in the substrate of a second conductivity type,with a channel region therebetween, a first insulation layer disposedover said substrate, an electrically conductive floating gate disposedover said first insulation layer and extending over a portion of thechannel region and over a portion of the first region, a secondinsulation layer disposed over and adjacent the floating gate and havinga thickness permitting Fowler-Nordheim tunneling of chargestherethrough, an electrically conductive control gate having a firstportion disposed adjacent to and insulated from the floating gate and asecond portion extending over a portion of the second insulation layerand a portion of the floating gate, the control gate having asubstantially vertical sidewall portion, and an insulation spacer formedadjacent to the substantially vertical sidewall portion of the controlgate. The second region has an edge that is aligned with thesubstantially vertical sidewall portion.

[0029] Other objects and features of the present invention will becomeapparent by a review of the specification, claims and appended figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIGS. 1A-1C are cross-sectional views of partially formed memorycells having control gates with sloping side wall profiles.

[0031]FIG. 2A is a top view of a semiconductor substrate used in thefirst step of the method of present invention to form isolation regions.

[0032]FIG. 2B is a cross sectional view of the structure of FIG. 2Ataken along the line 1-1.

[0033]FIG. 2C is a top view of the next step in the processing of thestructure of FIG. 2B, in which isolation regions are formed.

[0034]FIG. 2D is a cross sectional view of the structure in FIG. 2Ctaken along the line 1-1 showing the isolation stripes formed in thestructure.

[0035]FIG. 2E is a cross sectional view of the structure in FIG. 2Ctaken along the line 1-1 showing the two types of isolation regions thatcan be formed in the semiconductor substrate: LOCOS or shallow trench.

[0036] FIGS. 3A-3M are cross sectional views taken along the line 2-2 ofFIG. 2C showing in sequence the next step(s) in the processing of thestructure shown in FIG. 2C, in the formation of a non volatile memoryarray of floating memory cells of the split gate type.

[0037]FIG. 3N is a top view showing the interconnection of row lines andbit lines to terminals in active regions in the formation of the nonvolatile memory array of floating memory cells of the split gate type.

[0038] FIGS. 4A-4C are cross sectional views taken along the line 2-2 ofFIG. 2C showing in sequence the steps in a first alternate processing ofthe structure shown in FIG. 31, in the formation of a non volatilememory array of floating memory cells of the split gate type.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Referring to FIG. 2A there is shown a top plan view of asemiconductor substrate 10, which is preferably of P type and is wellknown in the art. A first layer of insulation material 12, such assilicon dioxide (oxide), is deposited thereon as shown in FIG. 2B. Thefirst insulation layer 12 is formed on the substrate 10 by well knowntechniques such as oxidation or deposition (e.g. chemical vapordeposition or CVD), forming a layer of silicon dioxide (hereinafter“oxide”). A first layer of polysilicon 14 (FG poly) is deposited on topof the first layer of insulation material 12. The deposition andformation of the first polysilicon layer 14 on the first insulationlayer 12 can be made by a well known process such as Low Pressure CVD orLPCVD. A silicon nitride layer 18 (hereinafter “nitride”) is depositedover the polysilicon layer 14, preferably by CVD. This nitride layer 18is used to define the active regions during isolation formation. Ofcourse, all of the forgoing described parameters and the parametersdescribed hereinafter, depend upon the design rules and the processtechnology generation. It will be understood by those skilled in the artthat the present invention is not limited to any specific processtechnology generation, nor to any specific value in any of the processparameters described hereinafter.

[0040] Once the first insulation layer 12, the first polysilicon layer14, and the silicon nitride 18 have been formed, suitablephoto-resistant material 19 is applied on the silicon nitride layer 18and a masking step is performed to selectively remove thephoto-resistant material from certain regions (stripes 16). Where thephoto-resist material 19 is removed, the silicon nitride 18, thepolysilicon 14 and the underlying insulation material 12 are etched awayin stripes 16 formed in the Y direction or the column direction, asshown in FIG. 2C, using standard etching techniques (i.e. anisotropicetch process). The distance W between adjacent stripes 16 can be assmall as the smallest lithographic feature of the process used. Wherethe photo resist 19 is not removed, the silicon nitride 18, the firstpolysilicon region 14 and the underlying insulation region 12 aremaintained. The resulting structure is illustrated in FIG. 2D. As willbe described, there are two embodiments in the formation of theisolation regions: LOCOS and STI. In the STI embodiment, the etchingcontinues into the substrate 10 to a predetermined depth.

[0041] The structure is further processed to remove the remaining photoresist 19. It should be noted that the above described etching ofpolysilicon 14, insulation material 12 and substrate 10 can be performedbefore or after photo resist 19 is removed. Then, an isolation material20 a or 20 b, such as silicon dioxide, is formed in the regions or“grooves” 16. The nitride layer 18 is then selectively removed to formthe structure shown in FIG. 2E. The isolation can be formed via the wellknown LOCOS process resulting in the local field oxide 20 a (e.g. byoxidizing the exposed substrate), or it can be formed via a shallowtrench isolation process (STI) resulting in silicon-dioxide being formedin the region 20 b (e.g. by depositing an oxide layer, followed by aChemical-Mechanical-Polishing or CMP etch). It should be noted thatduring the LOCOS formation, a spacer may be necessary to protect theside walls of poly layer 14 during the formation of the local fieldoxide.

[0042] The remaining first polysilicon layer 14 and the underlying firstinsulation material 12 form the active regions. Thus, at this point, thesubstrate 10 has alternating stripes of active regions and isolationregions with the isolation regions being formed of either LOCOSinsulation material 20 a or shallow trench insulation material 20 b.Although FIG. 2E shows the formation of both a LOCOS region 20 a and ashallow trench region 20 b, only one of the LOCOS process (20 a) or theshallow trench process (20 b) will be used. In the preferred embodiment,the shallow trench 20 b will be formed. Shallow trench 20 b ispreferable because it can be more precisely formed at smaller designrules.

[0043] The structure in FIG. 2E represents a self aligned structure,which is more compact than a structure formed by a non self-alignedmethod. A non self-aligned method of forming the structure shown in FIG.2E, which is well known and is conventional, is as follows. Regions ofisolation 20 are first formed in the substrate 10. This can be done bydepositing a layer of silicon nitride on the substrate 10, depositingphoto-resist, patterning the silicon nitride using a first masking stepto expose selective portions of the substrate 10, and then oxidizing theexposed substrate 10 using either the LOCOS process or the STI processwhere silicon trench formation and trench fill are involved. Thereafter,the silicon nitride is removed, and a first layer of silicon dioxide 12(to form the gate oxide) is deposited over the substrate 10. A firstlayer of polysilicon 14 is deposited over the gate oxide 12. The firstlayer of polysilicon 14 is then patterned using a second masking stepand selective portions removed. Thus, the polysilicon 14 is not selfaligned with the regions of isolation 20, and a second masking step isrequired. Further, the additional masking step requires that thedimensions of the polysilicon 14 have an alignment tolerance withrespect to the regions of isolation 20. It should be noted that the nonself-aligned method does not utilize nitride layer 18.

[0044] With the structure shown in FIG. 2E made using either the selfaligned method or the non self-aligned method, the structure is furtherprocessed as follows. Referring to FIG. 3A, which shows the structurefrom a view orthogonal to that of FIGS. 2B and 2E, the next steps in theprocess of the present invention are illustrated. An insulation layer22, such as nitride, is formed over the poly layer 14. A WL maskingoperation is performed with photo-resist applied on top of the nitridelayer 22. A masking step is applied in which stripes (i.e. maskingregions) are defined in the X or the row direction. The distance betweenadjacent stripes can be a size determined by the needs of the device tobe fabricated. The photo resist is removed in defined masking regions,i.e. stripes in the row direction, after which nitride layer 22underlying the removed photo resist is etched away in the stripes toexpose the underlying poly layer 14. For each pair of mirror memorycells to be formed, this etch process results in the formation of asingle first trench 24 that extends down to polysilicon layer 14. Theremaining photo-resist is then removed. This is followed by an oxidationprocess, which oxidizes the exposed portion of polysilicon layer 14inside of trenches 24 to form a lens shaped oxide layer 28 overpolysilicon layer 14. While not shown, an optional poly etch process canbe performed before the formation of layer 28. This optional customizedisotropic or sloped poly etch process etches away a portion of the topsurface of poly layer 14, but leaves a taper shape in that top surfacein the area next to the remaining nitride layer 22, with or without anundercut. Optional insulation side wall spacers 26 are then formed alongthe side wall surfaces of trenches 24. The formation of side wallspacers is well known in the art, by depositing a material over thecontour of a structure, followed by an anisotropic etch process (e.g.RIE), whereby the material is removed from horizontal surfaces of thestructure, while the material remains largely intact on verticallyoriented surfaces of the structure. Spacers 26 can be formed of anydielectric material. In the preferred embodiment, insulation spacers 26are formed of nitride. The resulting structure is shown in FIG. 3B.

[0045] Insulation (oxide) side wall spacers 30 are then formed insidetrenches 24 by depositing a thick layer of oxide, followed by ananisotropic oxide etch, which removes the deposited oxide except forspacers 30. This oxide etch step also removes the center portion ofoxide layer 28 from each of the trenches 24. An anisotropic poly etchprocess is performed between the opposing insulation spacers 30 toremove the exposed poly layer 14 at the bottom of trenches 24 until theoxide layer 12 is observed, which acts as an etch stop. An oxide etch isthen performed between spacers 30 to remove the thin oxide layer 12 atthe bottom of trenches 24 to expose substrate 10. The use of spacers 30allows the formation of trenches 24 having a width at the poly layer 14that is less than the width of the masking step used to initially definethe tops of trenches 24. The resulting structure is illustrated in FIG.3C.

[0046] The sides of polysilicon layer 14 and the substrate surfaces thatare exposed inside trenches 24 are oxidized in an oxidation step to formFG oxide side walls 32 on the sides of poly layer 14 and to reform oxidelayer 12 over the substrate. Alternately, an insulation layer can bedeposited followed by an anisotropic etch back process. Suitable ionimplantation is then made across the entire surface of the structure.Where the ions have sufficient energy to penetrate the first silicondioxide layer 12 in trench 24, they then form a first region (i.e.second terminal) 34 in the substrate 10. In all other regions, the ionsare absorbed by the existing structure, where they have no effect. Acontrolled oxide etch step is then performed to remove the centerportion of oxide layer 12 from each of the trenches 24 to expose thesubstrate 10. It should be noted that the ion implantation canalternately be performed after layer 12 is removed. The resultingstructure is shown in FIG. 3D.

[0047] A poly deposition step is then performed, followed by a polyplanarization (preferably by chemical-mechanical polishing (CMP)), tofill trenches 24 with poly blocks 36. A poly etchback step follows toremove excess polysilicon outside of trenches 24. The polysilicon isproperly doped either through an in-situ method or by conventionalimplantation. An oxide layer 38 is then formed over each of the polyblocks 36 in trenches 24 by thermal oxidation, which grows oxide layer38 only on poly blocks 36. A nitride etch is then performed to removenitride layer 22 and nitride spacers 26. An anisotropic poly etchfollows to remove the portion of poly layer 14 not covered by oxidespacers 30 and oxide layer 28. The poly etch effectively forms sharpedges 44 in poly layer 14. The nitride and poly etch steps effectivelycreate second trenches 40, one on either side of the mirror set ofmemory cells. An optional oxide etch can be performed to remove a smallportion of exposed oxide layer 28 to better expose sharp edge 44. Theresulting structure is shown in FIG. 3E.

[0048] The next step is an oxide formation process, which forms an oxidelayer 42 over the structure. Oxide layer 42 joins with oxide layer 28 toform an insulation layer that is disposed adjacent and over thepolysilicon layer 14, and upwardly projecting sharp edges 44 at eachside edge of polysilicon layer 14. The sharp edges 44 and the thicknessof the insulation layer formed by oxide layers 42/28, permitFowler-Nordheim tunneling of charges therethrough. A thick WL poly layer46 is formed over the structure (filling trenches 40), which is followedby the formation of a nitride layer 48 over the poly layer 46, asillustrated in FIG. 3F. Preferably, nitride layer 48 is 10-300 mn thick.For each memory cell pair, the resulting structure has a raised centralportion 49 a and lower side portions 49 b.

[0049] A planarization process follows, such as CMP, which removes thenitride layer 48 of the raised central portions 49 a, as shown in FIG.3G. The process is continued to remove the raised central portions ofpoly layer 46 and side portions of nitride layer 48 thereon, using oxidelayer 42 as an etch stop, as shown in FIG. 3H. It is preferred that theslurry chosen for CMP should not etch nitride, but rather etchpolysilicon only. Most of the mechanical polishing stress is applied tothe poly layer 46, and it is undesirable to have the slurry etch awaythe relatively thin nitride layer 48 on either side of the poly layer46. Preferably, the nitride layer 48 is removed mainly by mechanicalpolishing, so that once this CMP process is complete, portions ofnitride layer 48 on the lower side portions of poly layer 46 remainintact (to later serve as an oxidation protection layer).

[0050] Poly layer 46 is partially covered and protected by nitride layer48, with other portions that are left exposed by the CMP process. Alayer of oxide 50 is formed on those exposed portions of poly layer 46,preferably by an oxidation step, as shown in FIG. 3I. The oxide layer 50is preferably 8-80 mn thick. An anisotropic nitride etch processfollows, which removes nitride layer 48 from the horizontal surfaces ofthe structure, leaving nitride side wall spacers 52 over poly layer 46,as shown in FIG. 3J.

[0051] An anisotropic poly etch step is performed to remove the exposedportions of poly layer 46. The portions of poly layer 46 protected fromthe anisotropic etch process by oxide layer 50 and nitride spacers 52form blocks 54 of polysilicon 54, as shown in FIG. 3K. Poly blocks 54have vertical side walls 56 resulting from the anisotropic etch andprotective oxide layer 50. The vertical sidewalls are ideal for spacerformation as follows. Nitride side wall spacers 58 are formed adjacentvertical side walls 56 of poly blocks 54 by depositing nitride over thestructure followed by an anisotropic nitride etch (such as RIE dry etch)to remove all the added nitride except for side wall spacers 58, asshown in FIG. 3L. Side wall spacers 58 not only insulate poly blocks 54,but also facilitate the formation of self aligned salicide and contactsfor the second regions as described next. Ion implantation (e.g. N+) isused to form second regions (i.e. first terminals) 60 in the substratein the same manner as the first regions 34 were formed, as shown in FIG.3M. A thin oxide etch is performed to remove any exposed portions ofoxide layers 12 and 42 over substrate 10, and oxide layers 38, 42 and 50over the structure. A metal deposition step is then performed, todeposit a metal such as tungsten, cobalt, titanium, nickel, platinum, ormolybdenum over the structure. The structure is then annealed,permitting the metal to react with the exposed top portions of thesubstrate 10 and poly blocks 36/54 to form a conductive layer ofmetalized silicon 62 (silicide) on the substrate next side wall spacers58, and a conductive layer of metalized silicon 63 over the poly blocks36 and 54. Metalized silicon regions 62 on substrate 10 can be calledself aligned silicide (i.e. salicide), because they are self aligned tothe second regions 60 by spacers 58. Metalized silicon regions 63facilitate conduction along the connected rows of poly blocks 36 and 54.The unreacted metal deposited on the remaining structure is removed by ametal etch process.

[0052] Passivation, such as BPSG 64, is used to cover the entirestructure. A masking step is performed to define etching areas over thesalicide regions 62. The BPSG 64 is selectively etched in the maskedregions to create contact openings that are ideally centered over andwider than the salicide regions 62 formed between adjacent sets ofpaired memory cells. Nitride spacers 52 and 58 serve to protect polyblocks 54 from this etch process. The contact openings are then filledwith a conductor metal 66 by metal deposition and planarizing etch-back,whereby the entire area between nitride spacers 58 of adjacent sets ofpaired memory cells is filled with the deposited metal to form contactconductors 66 that are self aligned to the salicide regions 62 by thenitride spacers 58 (i.e. self aligned contact scheme, or SAC). Thesalicide layers 62 facilitate conduction between the conductors 66 andsecond regions 60. Bit lines 68 are added by metal masking over the BPSG64, to connect together all the conductors 66 in each column of memorycells. The final memory cell structure is illustrated in FIG. 3M.

[0053] The self aligned contact scheme (SAC) removes an importantconstraint on the minimum spacing requirement between adjacent sets ofpaired memory cells. Specifically, while FIG. 3M illustrates the contactarea (and thus conductors 66) perfectly centered over the salicideregions 62, in reality it is very difficult to form the contact openingswithout some undesirable horizontal shift relative to the salicideregions 62. With a non-self aligned contact scheme, where there is noprotective insulation layer over the structure before BPSG formation,electrical shorts can occur if the contact 66 is shifted over and formedover poly block 54. To prevent electrical shorts in a non-self alignedcontact scheme, the contact openings would have to be formedsufficiently away from the nitride spacers 58 so that even with themaximum possible shift in the contact regions, they will not extend tonitride spacers 58 or beyond. This of course would present a constrainton the minimum distance between spacers 58, in order to provide asufficient tolerance distance between adjacent sets of paired mirrorcells.

[0054] The SAC method of the present invention eliminates thisconstraint by forming the protective layer of material (nitride spacers52 and 58) underneath the BPSG. With this protective layer, the contactopenings are formed in the BPSG with a sufficient width to ensure thereis overlap of the contact opening with the salicide regions 62, even ifthere is a horizontal shift of the contact opening during formation.Nitride spacers 52 and 58 allow portions of contacts 66 to be formedover poly blocks 54 without any shorting therebetween. The wide contactopening guarantees that contacts 66 completely fill the very narrowspaces between spacers 58, and makes good electrical contact withsalicide regions 62. Thus, the width of contact regions between spacers58 can be minimized to allow the scaling down of the overall celldimension.

[0055] As shown in FIG. 3M, first and second regions 34/60 form thesource and drain for each cell (those skilled in the art know thatsource and drain can be switched during operation). A channel region 70for each cell is defined as the portion of the substrate that isin-between the source and drain 34/60. Poly blocks 54 constitute thecontrol gates, and poly layer 14 constitutes the floating gate. Thecontrol gates 54 are generally rectangular in shape, but with a lowerfirst portion 72 that is disposed adjacent the floating gate 14(insulated therefrom by oxide layer 42), and an upper second portion 74that protrudes over a portion of floating gate 14 and forms a notch 76.The sharp edge 44 of floating gate 14 extends into the notch 76.Floating gate 14 is over part of the channel region 70, is partiallyoverlapped at one end by the control gate 54, and partially overlaps thefirst region 34 with its other end. As illustrated in the FIG. 3M, theprocess of the present invention forms pairs of memory cells that mirroreach other. Each pair of mirrored memory cells is insulated fromadjacent pairs of mirrored memory cells by nitride spacers 58.

[0056] Referring to FIG. 3N, there is shown a top plan view of theresulting structure and the interconnection of the bit lines 68 to thesecond regions 60 and of the control lines 54 which run in the X or therow direction and finally the source lines 36 which connect to the firstregions 34 within the substrate 10. Although the source lines 36 (asshould be understood by those skilled in the art, the word “source” isinterchangeable with the word “drain”) make contact with the substrate10 in the entire row direction, i.e. contact with the active regions aswell as the isolation regions, the source lines 36 electrically connectonly to the first regions 34 in the substrate 10. In addition, eachfirst region 34 to which the “source” line 36 is connected is sharedbetween two adjacent memory cells. Similarly, each second region 60 towhich the bit line 68 is connected is shared between adjacent memorycells from different mirror sets of memory cells.

[0057] The result is a plurality of non volatile memory cells of thesplit gate type having a floating gate 14, a control gate 54 which isimmediately adjacent to but separated from the floating gate 14 andconnected to a substantially rectangularly shaped structure which runsalong the length of the row direction connecting to the control gates ofother memory cells in the same row, a source line 36 which also runsalong the row direction, connecting the first regions 34 of pairs ofmemory cells in the same row direction, and a bit line 68 which runsalong the column or Y direction, connecting the second regions 60 ofpairs of memory cells in the same column direction. The formation of thecontrol gate, the floating gate, the source line, and the bit line, areall self-aligned. A key feature of the present invention is theformation of a protective layer or layers over the polysilicon thatforms the control gates, and etching the remaining unprotectedpolysilicon so that the control gates each have a vertical sidewall thatis conducive to spacer formation. The non-volatile memory cell is of thesplit gate type having floating gate to control gate tunneling asdescribed in U.S. Pat. No. 5,572,054, whose disclosure is incorporatedherein by reference with regard to the operation of such a non-volatilememory cell and an array formed thereby.

[0058] FIGS. 4A-4C illustrate an alternate process for forming a memorycell array similar to that illustrated in FIG. 3M, but without the useof spacers 52 in the finished device. This alternate process begins withthe same structure as shown in FIG. 31, but continues as follows.Instead of an anisotropic nitride etch which results in spacers 52, anisotropic nitride etch is used to remove all of nitride layer 48, asillustrated in FIG. 4A.

[0059] An anisotropic poly etch step is then performed to remove theexposed portions of poly layer 46, which leaves blocks of polysilicon 54underneath oxide layer 50, as shown in FIG. 4B. Poly blocks 54 havevertical side walls 56 that are conducive to spacer formation, and areinsulated from above by oxide layer 50. Nitride side wall spacers 58 arethen formed adjacent vertical side walls 56 of poly blocks 54 bydepositing nitride over the structure followed by an anisotropic nitrideetch (such as RIE dry etch) to remove all the added nitride except forside wall spacers 58, as shown in FIG. 4C. Poly blocks 54 are fullyinsulated from above by oxide layer 50 and from the side by nitridespacers 58. Side wall spacers 58 not only insulate poly blocks 54, butalso facilitate the formation of salicide and contacts for the secondregions. The remaining steps discussed above with respect to thepreferred embodiment are then performed to complete the memory cellarray.

[0060] It is to be understood that the present invention is not limitedto the embodiments described above and illustrated herein, butencompasses any and all variations falling within the scope of theappended claims. For example, although the foregoing method describesthe use of appropriately doped polysilicon as the conductive materialused to form the memory cells, it should be clear to those havingordinary skill in the art that any appropriate conductive material canbe used. In addition, any appropriate insulator can be used in place ofsilicon dioxide or silicon nitride. Moreover, any appropriate materialwhose etch property differs from silicon dioxide (or any insulator) andfrom polysilicon (or any conductor) can be used in place of siliconnitride. Further, as is apparent from the claims, not all method stepsneed be performed in the exact order illustrated or claimed, but ratherin any order that allows the proper formation of the memory cell of thepresent invention.

What is claimed is:
 1. A self-aligned method of forming a semiconductormemory array of floating gate memory cells in a semiconductor substrate,each memory cell having a floating gate, a first terminal, a secondterminal with a channel region therebetween, and a control gate, themethod comprising the steps of: a) forming a plurality of spaced apartisolation regions on the substrate which are substantially parallel toone another and extend in a first direction, with an active regionbetween each pair of adjacent isolation regions, the active regions eachcomprising a first layer of insulation material on the semiconductorsubstrate and a first layer of conductive material on the first layer ofinsulation material; b) forming a plurality of spaced apart blocks ofinsulation material in each of the active regions and over the firstlayer of conductive material; c) forming a plurality of spaced apartblocks of conductive material in each of the active regions that areeach disposed over and insulated from the substrate and adjacent to oneof the blocks of insulation material; d) forming a protective layer ofmaterial over a first portion of each of the blocks of conductivematerial, wherein a second portion of each of the blocks of conductivematerial is left uncovered by the layer of protective material; e)etching away the second portions of the blocks of conductive material toform a substantially vertical sidewall portion on each of the blocks ofconductive material; f) forming a plurality of first terminals in thesubstrate, wherein in each of the active regions each of the firstterminals has a side edge that is aligned to one of the substantiallyvertical sidewall portions; and g) forming a plurality of secondterminals in the substrate, wherein in each of the active regions eachof the second terminals is spaced apart from the first terminals.
 2. Themethod of claim 1, wherein one of the blocks of conductive material ineach of the active regions extends across adjacent isolation regions andis electrically connected with blocks of conductive material formed inadjacent active regions.
 3. The method of claim 1, further comprisingthe steps of: removing the protective layer of material from the blocksof conductive material, and forming a layer of metalized silicon on theblocks of conductive material.
 4. The method of claim 1, wherein thefirst layer of conductive material is formed with a plurality of sharpedges each extending toward one of the blocks of conductive material. 5.The method of claim 1, wherein the formation of the protective layerincludes the steps of: forming a layer of insulation material over thesecond portions of the blocks of conductive material; and forming aspacer of insulation material over at least part of the first portionsof the blocks of conductive material.
 6. The method of claim 1, whereineach of the first portions of the blocks of conductive material includesa lower portion that is disposed adjacent to and insulated from thefirst layer of conductive material.
 7. The method of claim 6, whereineach of the first portions of the blocks of conductive material includesan upper portion that extends over and is insulated from a portion ofthe first layer of conductive material.
 8. The method of claim 7,wherein each of the first portions of the blocks of conductive materialforms a control gate having a notch formed underneath the upper portion.9. The method of claim 1, further comprising the steps of: forming aside wall spacer of insulating material along each of the substantiallyvertical sidewall portions; and forming a layer of metalized silicon ineach of the first terminals immediately adjacent to one of the side wallspacers, wherein each of the layers of metalized silicon is self-alignedto the one of the first terminals by one of the side wall spacers. 10.The method of claim 9, further comprising the step of: forming aconductive material over each of the first terminals and against theside wall spacer self aligning one of the layers of metalized siliconthereto.
 11. The method of claim 1, further comprising the steps of:forming a side wall spacer of insulating material along each of thesubstantially vertical sidewall portions such that pairs of the sidewall spacers are adjacent to but spaced apart from each other with oneof the first terminals substantially therebetween; forming a layer ofmetalized silicon in each one of the first terminals between a pair ofthe side wall spacers corresponding to the one first terminal such thatthe layer of metalized silicon is self-aligned to the one first terminalby the corresponding pair of side wall spacers; forming a layer ofpassivation material over the active regions; forming contact openingsthrough the passivation material, wherein for each of the contactopenings: the contact opening extends down to and exposes one of themetalized silicon layers, the contact opening has a lower portionbounded by the corresponding pair of side wall spacers, and the contactopening has an upper portion that is wider than a spacing between thecorresponding pair of side wall spacers; and filling each of the contactopenings with a conductive material.
 12. A self-aligned method offorming a semiconductor memory array of floating gate memory cells in asemiconductor substrate, each memory cell having a floating gate, afirst terminal, a second terminal with a channel region therebetween,and a control gate, the method comprising the steps of: a) forming aplurality of spaced apart isolation regions on the substrate which aresubstantially parallel to one another and extend in a first direction,with an active region between each pair of adjacent isolation regions,the active regions each comprising a first layer of insulation materialon the semiconductor substrate and a first layer of conductive materialon the first layer of insulation material; b) forming a plurality ofspaced apart first trenches across the active regions and isolationregions which are substantially parallel to one another and extend in asecond direction that is substantially perpendicular to the firstdirection and exposing the first layer of the conductive material ineach of the active regions; c) forming first side wall spacers of amaterial on side walls of the first trenches; d) forming a second sidewall spacer of a material on each of the first side wall spacers; e)forming second trenches in each of the active regions adjacent to thefirst trenches, wherein the formation of the second trenches includesremoving the first side wall spacers; f) filling each of the secondtrenches with a second conductive material to form blocks of conductivematerial; g) forming a protective layer of material over a first portionof each of the blocks of conductive material, wherein a second portionof each of the blocks of conductive material is left uncovered by thelayer of protective material; h) etching away the second portions of theblocks of conductive material to form a substantially vertical sidewallportion on each of the blocks of conductive material; i) forming aplurality of first terminals in the substrate, wherein in each of theactive regions each of the first terminals has a side edge that isaligned to one of the substantially vertical sidewall portions; and j)forming a plurality of second terminals in the substrate, wherein ineach of the active regions each of the second terminals is spaced apartfrom the first terminals.
 13. The method of claim 12, wherein one of theblocks of conductive material in each of the active regions extendsacross adjacent isolation regions and is electrically connected withblocks of conductive material formed in adjacent active regions.
 14. Themethod of claim 12, further comprising the steps of: removing theprotective layer of material from the blocks of conductive material, andforming a layer of metalized silicon on the blocks of conductivematerial.
 15. The method of claim 12, wherein the first layer ofconductive material is formed with a plurality of sharp edges eachextending toward one of the blocks of conductive material.
 16. Themethod of claim 12, wherein for each of the blocks of conductivematerial: the block is insulated from the substrate, and the blockincludes a protruding portion, formed by an indentation in the secondtrench side wall, that is disposed over and insulated from the firstlayer of conductive material.
 17. The method of claim 16, wherein eachof the first portions of the blocks of conductive material forms acontrol gate having a notch underneath the protruding portion.
 18. Themethod of claim 12, wherein a lower portion of each of the firstportions of the blocks of conductive material is disposed adjacent toand insulated from the first layer of conductive material.
 19. Themethod of claim 12, wherein the formation of the first trenchescomprises the steps of: forming at least one layer of material over thefirst layer of conductive material; selectively etching through the atleast one layer of material to form top portions of the first trenches,wherein the first and second spacers are then formed in the firsttrenches; and etching between the second side wall spacers in each ofthe first trenches and through the first layer of conductive material toform bottom portions of the first trenches; wherein the bottom portionsof the first trenches have a smaller width than that of the top portionsof the first trenches.
 20. The method of claim 12, further comprisingthe steps of: forming a third side wall spacer of insulating materialalong the substantially vertical side wall portion of each of the blocksof conductive material; and forming a layer of metalized silicon in eachof the second terminals immediately adjacent to one of the third sidewall spacers, wherein the layer of metalized silicon is self-aligned tothe one third side wall spacer.
 21. The method of claim 20, furthercomprising the step of: forming a conductive material over each of thefirst terminals and against the third side wall spacer self aligning oneof the layers of metalized silicon thereto.
 22. The method of claim 12,further comprising the steps of: forming a third side wall spacer ofinsulating material along each of the substantially vertical sidewallportions such that pairs of the third side wall spacers are adjacent tobut spaced apart from each other with one of the first terminalssubstantially therebetween; forming a layer of metalized silicon in eachone of the first terminals between a pair of the third side wall spacerscorresponding to the one first terminal such that the layer of metalizedsilicon is self-aligned to the one first terminal by the correspondingpair of third side wall spacers; forming a layer of passivation materialover the active regions; forming contact openings through thepassivation material, wherein for each of the contact openings: thecontact opening extends down to and exposes one of the metalized siliconlayers, the contact opening has a lower portion bounded by thecorresponding pair of third side wall spacers, and the contact openinghas an upper portion that is wider than a spacing between thecorresponding pair of third side wall spacers; and filling each of thecontact openings with a conductive material.
 23. An electricallyprogrammable and erasable memory device comprising: a substrate ofsemiconductor material of a first conductivity type; first and secondspaced-apart regions in the substrate of a second conductivity type,with a channel region therebetween; a first insulation layer disposedover said substrate; an electrically conductive floating gate disposedover said first insulation layer and extending over a portion of thechannel region and over a portion of the first region; a secondinsulation layer disposed over and adjacent the floating gate and havinga thickness permitting Fowler-Nordheim tunneling of chargestherethrough; an electrically conductive control gate having a firstportion disposed adjacent to and insulated from the floating gate and asecond portion extending over a portion of the second insulation layerand a portion of the floating gate, the control gate having asubstantially vertical sidewall portion; and an insulation spacer formedadjacent to the substantially vertical sidewall portion of the controlgate; wherein the second region has an edge that is aligned with thesubstantially vertical sidewall portion.
 24. The device of claim 23,further comprising: a third insulation layer formed over a top surfaceof the control gate.
 25. The device of claim 23, wherein the floatinggate includes a sharp edge portion that extends toward the control gate.26. The device of claim 25, the first and second portions of the controlgate form a notch into which the sharp edge portion of the floating gateextends.
 27. The device of claim 23, further comprising: a layer ofmetalized silicon formed on the second region and aligned to theinsulation spacer.
 28. An array of electrically programmable anderasable memory devices comprising: a substrate of semiconductormaterial of a first conductivity type; spaced apart isolation regionsformed on the substrate which are substantially parallel to one anotherand extend in a first direction, with an active region between each pairof adjacent isolation regions; each of the active regions including acolumn of memory cells extending in the first direction, each of thememory cells including: first and second spaced-apart regions formed inthe substrate having a second conductivity type, with a channel regionformed in the substrate therebetween, a first insulation layer disposedover said substrate including over said channel region, an electricallyconductive floating gate disposed over said first insulation layer andextending over a portion of the channel region and over a portion of thefirst region, and a second insulation layer disposed over and adjacentthe floating gate and having a thickness permitting Fowler-Nordheimtunneling of charges therethrough; and a plurality of electricallyconductive control gates each extending across the active regions andisolation regions in a second direction substantially perpendicular tothe first direction and having a first portion and a second portion,wherein each of the control gates intercepts one of the memory cells ineach of the active regions such that the first portion is positionedadjacent to the second insulation layer and the floating gate and thesecond portion partially extends over the second insulation layer andthe floating gate, and wherein each of the control gates has asubstantially vertical sidewall portion; and a plurality of insulationspacers each formed adjacent to one of the substantially verticalsidewall portions of the control gates; wherein the second region has anedge that is aligned with the substantially vertical sidewall portion.29. The device of claim 28, further comprising: a third insulation layerformed over a top surface of each of the control gates.
 30. The deviceof claim 28, wherein each of the floating gates includes a sharp edgeportion that extends toward one of the control gates.
 31. The device ofclaim 30, wherein for each of the control gates, the first and secondportions form a notch into which the sharp edge portion of the floatinggate extends.
 32. The device of claim 28, further comprising: a layer ofmetalized silicon formed on each of the second regions and aligned tothe corresponding insulation spacer.